Increase of a number of components due to advanced functions of electronic apparatus and development of miniaturizing or slimming of the apparatus also require miniaturizing or slimming of semiconductor packages themselves. As a semiconductor package suitable for mobile apparatus which are required to be downsized there is a BGA (Ball Grid Array) or CSP (Chip Size Package) as disclosed in Patent Document 1, for example. As shown in FIG. 7 (symbols in FIG. 7 are explained in the figure, added by 100) solder balls are arranged in a grid pattern at the bottom of the package as terminals and this kind of semiconductor package is widely utilized because more terminals can be provided in a narrow area.
Recently a chip-stack type semiconductor package, that is, a plurality of semiconductor chips are stacked in the semiconductor package, is being utilized and particularly plays an important role for mobile apparatuses.
One problem is a high cost of the semiconductor package stacking a plurality of semiconductor chips in the package because a yield after packaging step becomes extremely low when the stacked semiconductor chips are not well inspected or when semiconductor chips which may cause low yields are combined.
Particularly, when using semiconductor chips purchased from other companies further own inspections are necessary to guarantee the quality of the semiconductor chips because the quality of the semiconductor chips themselves cannot be guaranteed to the same extent of the semiconductor packages. Therefore, provision for inspection devices and inspection programs are necessary, which results in higher manufacturing costs.
Thus the applicant proposed a semiconductor package structure of stack-packaged type as shown in FIG. 8 (symbols in FIG. 8 are explained in the figure, added by 100) (Patent Document 2). To manufacture the semiconductor package structure a plurality of semiconductor chips are packaged, then these packages are inspected separately and finally the packages are stacked to form a semiconductor package structure.    [Patent Document 1] JP-Patent No. 3395164    [Patent Document 2] JP Patent Kokai Publication No. JP-P2004-146751A